Pearl Semiconductor

Senior Digital Design Engineer

Job Code: EG_SDE_7/25

Location: Cairo, Egypt

Employment Type: Full Time

Responsibilities:

Design and implement complex digital circuits using Verilog/SystemVerilog.
Work on advanced timing IC designs and clock generation circuits.
Perform RTL-to-GDS implementation including timing closure and physical verification.
Develop comprehensive verification testbenches using UVM methodology.
Drive design optimization for performance, power, and area in advanced nodes.

Qualifications:

3-5 years of experience in digital design.
Proven experience in digital design with strong RTL design proficiency.
Hands-on experience with PnR tools (Innovus, or ICC2).
Expertise in verification methodologies (UVM, SystemVerilog, formal verification).
Experience with design constraints and timing closure.
Knowledge of timing analysis and clock domain crossing.
Experience with mixed-signal design flows (preferred).
Experience with Design for Test (DFT) methodologies is a plus.
Experience with Python development is a plus.
Experience with Silicon bring up and characterization is a plus.

For interested applicants, please send your resume to hr.eg@pearlsemi.com mentioning the Job Code in the subject of the email.

Pearl Semiconductor offers a competitive financial package along with a medical insurance plan that covers the employee and his/her immediate family members.

Pearl Semiconductor is an Equal Opportunity Employer.

Contact Us

Pearl Semiconductor B.V.

Hoogoorddreef 15, Amsterdam, 1101 BA, Netherlands.

Phone

+31 20 522 2555

hq@pearlsemi.com

Pearl Semiconductor Egypt

3, Khaled Ibn Al-Waleed Street, Sheraton Heliopolis, Cairo 11361, Egypt.

Phone

+202 22690075

info@pearlsemi.com